Younes Boulghassoul

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— Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upsetting the logic state of memory circuits. In this paper we investigate the critical charge (Q crit) required to upset a 6T SRAM cell designed in a commercial 90nm process. We(More)
This work presents an efficient hybrid simulation approach, developed for accurate characterization of single-event transients (SETs) in combinational logic. Using this approach, we show that charges as small as 3.5fC can introduce transients in commercial 90nm CMOS technology, hence increasing the likelihood of SET-induced soft errors. SET pulse-widths as(More)
SRAM reliability faces serious challenges due to radiation-induced soft errors in aggressively scaled CMOS technologies. The increasing frequency of single-bit upsets and more recently multi-bit upsets (MBU) limits the efficacy of conventionally used single-bit error correcting codes (ECC). Additionally, techniques used in achieving dense packing of SRAM(More)
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