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We propose a near optimal hardware architecture for deblocking filter in H.264/MPEG-4 AVC. We propose a novel filtering order and a data reuse strategy that result in significant saving in filtering time, local memory usage, and memory traffic. Every 16x16 macroblock requires 192 filtering operations. After a few initialization cycles, our 5-stage pipelined(More)
We propose a graph-theoretic approach for the data path allocation problem. We decompose the problem into three subproblems: (1) register allocation, (2) operation assignment, and (3) connection allocation. The first two subproblems are modeled as two bipartite weighted matching problems and solved using the Hungarian Method [Pap82]. The third subproblem is(More)
We present an algorithm for pipelining loop execution in the presence of loop catried dependence. We optimize both the initiation interval and the turn around time of a schedule. Given constraints on the number of functional units and buses, we tirst determine an initiation interval and then incremen-tally partition the operations into blocks to fit into(More)
—We propose a hardware accelerator for Context-based Adaptive Binary Arithmetic decoding (CABAC) in H.264/AVC. We also propose an efficient memory system for easy integration with other components such as motion compensation and IDCT. We develop an efficient finite state machine so that our design can generate one bit every 2 to 3 clock cycles. Experimental(More)
The test scheduling of memory cores can significantly affect the test time and power of system chips. We propose a test scheduling algorithm for BISTed memory cores to minimize the overall testing time under the test power constraint. The proposed algorithm combines several approaches for a near-optimal result, based on the properties of BISTed memory(More)