Youichi Ikeda

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In sub 1 V CMOS VLSIs, the authors proposed a new body bias generation circuits in which Ids and Vt of pMOS/nMOS become always fixed. The mixed body bias techniques result in positive temperature dependence of the delay, 85% reduction of the delay variation, and 75% improvement of power consumption of SRAM on a mobile processor.
This paper presents the boundary-type schemes of the first-and the second-order sensitivity analyses by Trefftz method. In the Trefftz method, physical quantities are approximated by the superposition of the T-complete functions satisfying the governing equations. Since the T-complete functions are regular, the approximate expressions of the quantities are(More)
We have developed a 32-bit, 64-word 9-read, 7-write ported register file for a processor based on 130 nm process technology. This register file has several circuits for improving noise and process variation tolerance, such as self-timing control circuits and crosstalk reduction circuits. Body bias voltage control can also be employed. These circuits and(More)
An improved symmetric GaAs MESFET structure with a lightly doped deep source/drain is proposed for application to power amplifiers in mobile communication terminals. With lightly doped deep drain, the impact ionization falls as the electron current expands and the current density decreases. Thus, the breakdown voltage rises, while a high transconductance(More)
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