Yoshiaki Toyoshima

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In this paper, detailed analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET are described. The FinFET with narrow fin width such as below 30 nm is attractive for scaled CMOS because of double gate structure. Additionally, the flicker noise of FinFET decreases and the temperature dependence of the noise become smaller as the fin(More)
This paper presents a detailed analysis of latch-up characteristics for 90nm RF CMOS on high-resistivity substrate with 400 ohm-cm for the first time. According to our measurement and simulation results, latch-up dependence of PNP base and NPN emitter injection mode on Si substrate resistivity is small. On the other hand, PNP emitter and NPN base injection(More)
High-resistivity substrate with beyond 1000 ohm-cm realizes high performance in terms of inductor, antenna, MIM capacitor and substrate noise for high- frequency applications. However, this wafer has serious problems for mixed-signal, RF and digital circuits. Those are reduction of high resistivity during sinter process such as 400degC, larger leakage(More)
Si surface properties and electrical characteristics in n- and p-MOSFETs with 2-6 degree tilted off-axis (110) channel were investigated for the first time. The transconductance of p-MOSFET with off-axis channel was significantly degraded than that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved than that of normal channel.(More)
—We present a compact and efficient Monte Carlo method to reproduce a size effect on resistivity in sub-0.1μm metallic interconnects. Implementation of our method is easy and our method is also not CPU-intensive thanks to its compactness and simplicity. In our method, the geometric effect of the size effect can be taken into account since surface scattering(More)
Theoretical analyses predict that large Schottky barrier reduction by sulfur doping at NiSi/Si junction is induced by S2 formation. The S2 formation may have occurred in silicidation process, even under low temperature rapid thermal annealing. We have demonstrated that implanted sulfur into silicon forms S2 configuration under low temperature rapid thermal(More)
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