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In order to automate routine fecal examination for parasitic diseases, we propose in this study a computer processing algorithm using digital image processing techniques and an artificial neural network (ANN) classifier. The morphometric characteristics of eggs of human parasites in fecal specimens were extracted from microscopic images through digital(More)
A computer-aided diagnosis (CAD) algorithm identifying breast nodule malignancy using multiple ultrasonography (US) features and artificial neural network (ANN) classifier was developed from a database of 584 histologically confirmed cases containing 300 benign and 284 malignant breast nodules. The features determining whether a breast nodule is benign or(More)
Recently Network-on-Chip (NoC) technique has been proposed as a promising solution for on-chip interconnection network. However , different interface specification of integrated components raises a considerable difficulty for adopting NoC techniques. In this paper, we present a generic architecture for network interface (NI) and associated wrappers for a(More)
WaveSync is a network-on-chip architecture for a globally asynchronous locally-synchronous (GALS) design. The WaveSync design facilitates low-latency communication leveraging the source-synchronous clock sent along with the data to time components in the datapath of a downstream router, reducing the number of synchronizations needed. WaveSync accomplishes(More)
The computational performance of Network-on-Chip (NoC) and Multi-Processor System-on-Chip (MPSoC) for implementing cryptographic block ciphers can be improved by exploiting parallel and pipeline execution. In this paper, we present a parallel and pipeline processing method for block cipher algorithms: Data Encryption Standard (DES), Triple-DES Algorithm(More)
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either traditional or multi-layer bus architectures because of their poor scalability and bandwidth limitation on a single bus. While new interconnection techniques have been explored to(More)
This article presents a low-power decoder design for joint source-channel decoding (JSCD) based on a novel unequal error protection (UEP) scheme over additive white gaussian noise (AWGN) channels. Conventional JSCD schemes, adopting low-density parity check (LDPC) codes for multimedia devices, typically operate at a fixed-time decoding loop, regardless of(More)