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This paper proposes a class-E power amplifier (PA) with double-resonance circuit to reduce voltage stress on CMOS transistors. The voltage waveform applied to the CMOS transistor is shaped by harmonic control and the transistors are relieved from breakdowns. A negative capacitance is also implemented for efficiency enhancement, compensating for surplus(More)
An X-band power amplifier (PA) based on the pulsed load modulation (PLM) architecture is developed. The PLM technique leverages on the load modulation characteristics incurred for modulated pulses with different duty cycles as the consequence of the interactions between switching PAs with the high-Q output filter. Though a high drain efficiency is promised(More)
This paper proposes class-E power amplifier including negative capacitance to optimize shunt drain capacitance. The negative capacitance improves efficiency, compensates for surplus shunt drain capacitance resulting from parasitic capacitance, and is implemented without an external circuit. A cascode single-ended class-E RF power amplifier including driver(More)
Bitstream transmitters based on bandpass or envelope delta–sigma modulation promise high power efficiency for broadband communications with nonconstant-envelope modulations, but at the price of elevated quantization noise. An active noise filtering technique is proposed in this paper to address the quantization noise issue of such transmitters. The(More)
Switched mode RF power amplifiers (PAs) under bitstream modulations, such as bandpass or envelope delta-sigma modulations (EDSMs), have received increasing attentions over the past years. Such amplifiers offer high power efficiencies under power back-off conditions with pulse train voltage waveforms yet maintain their linearity in amplification through(More)
Digital switching-mode power amplifiers (PA) based on bit-stream modulations such as Delta Sigma Modulations (DSM) have been studied as a potential solution to overcome the trade-off between the power efficiency and the signal linearity of RF PAs. FIR filtering has been introduced to suppress the quantization noise near signal band for those transmitters(More)
—This paper presents a fast received signal strength indicator (RSSI) circuit for wireless communication application. The proposed circuit is developed using power detectors and an analog-to-digital converter to achieve a fast settling time. The power detector is consisted of a novel logarithmic variable gain amplifier (VGA), a peak detector, and a(More)
SUMMARY This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13 μm standard CMOS technology and the experimental results(More)
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