Yongguang Xiao

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Key Laboratory for Low Dimensional Materials and Application Technology of Ministry of Education (Xiangtan University), Xiangtan, Hunan 411105, China ASIC R&D Center, School of Electronic Science and Engineering of National University of Defense Technology, Changsha, Hunan 410073, China Pacific Geoscience Centre, Geological Survey of Canada, 9860 West(More)
A new methodology of layout design applying Euler path is proposed. By separating the pFET array and nFET array away, and then mapping them to be diffusion graphs, we can reduce the operational complexity when solving Euler path and generating the stacked layout. The means that making use of adjacency matrix of diffusion graph to identify Euler path and(More)
The transient effect of graded channel partially-depleted silicon-on-insulator nMOSFETs are analyzed by SILVACO ATLAS software. The switch on and switch off transient behaviors are studied for the device. While the device operates in the kink region, the transient effects of drain current were also investigated. It was found that the transient(More)
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