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— The earliest and the most critical stage in VLSI layout design is the placement. The background of which is the rectangle packing problem: Given set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area. Since the variety of the packing is uncountably infinite, the key issue for successful(More)
A new method of packing the rectangles (modules) is presented with applications to IC layout design. It is based on the bounded-sliceline grid (BSG) structure. The BSG dissects the plane into rooms associated with binary relations ``right-to''and ``above'' such that any two rooms are uniquely in either relation. A packing is obtained through an assignment(More)
The first and the most critical stage in VLSI layout design is the placement, the background of which is the rectangle packing problem: Given many rectangular modules of arbitrary size, place them without overlapping on a layer in the smallest bounding rectangle. Since the variety of the packing is infinite (two- dimensionally continuous) many, the key(More)
Routing for high speed boards is still achieved manually nowadays. There have been some related works in escape routing to solve this problem recently, however a more practical problem is not addressed. Usually the packages/components are designed with or without the requirement from board designers, and the boundary pins are usually fixed or advised to(More)
—A floorplan of a bounding box is its dissection into rectangles (rooms) by horizontal and vertical segments. This paper proposes a string data structure called the Quarter-state sequence (or Q sequence) to represent the floorplan. The Q sequence is a con-catenation of the states of rooms along the Abe order and is related to the VH graph, which is the(More)
After the discussion on the difference between floorplanningand packing in VLSI placement design, this paperadapts the floorplanner that is based on the Q-sequence to apacking algorithm. For the purpose, some empty room insertionis required to guarantee not to miss the optimum packing.To increase the performance in packing, a new move that perturbsthe(More)
| It is known that the clock-period in a sequential circuit can be shorter than the maximum signal delay between registers if the clock arrival time to each register is controlled. We propose an algorithm to nd the minimum clock-period of a circuit whose signal propagation delays are given. Experimental results on LGSynth93 benchmarks show that this(More)