Yoichi Taira

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As device-scaling challenges increase, three-dimensional (3D) integrated circuits (ICs) are receiving more attention for system performance enhancements, due to their higher interconnect densities and shorter interconnect lengths. However, because of the limited contact area and the higher circuit density, the cooling of 3D ICs is more challenging. In order(More)
We have developed a new technique for generating homogeneously distributed irregular dot patterns useful for optical devices and digital halftoning technologies. To introduce irregularity, we use elaborately designed sequences called low-discrepancy sequences instead of pseudorandom numbers. We also use a molecular-dynamics redistribution method to improve(More)
The high cost and low scalability of interfacing standard optical fibers to nanophotonic waveguides hinder the deployment of silicon photonics. We propose a mechanically compliant low-cost interface with integrated polymer waveguides. Our concept promises better mechanical reliability than a direct fiber-to-chip coupling and a dramatically larger bandwidth(More)
Building blocks and experimental results of an optical card-backplane-card link with waveguides embedded into the boards and butt-coupled optoelectronic modules are presented. Important next steps for acceptance of the technology by system developers are listed.
Silicon nanophotonics may bring disruptive advances to datacom, telecom, and high performance computing. However, the deployment of this technology is hampered by the difficulty of cost efficient optical inputs and outputs. To address this challenge, we have recently proposed a low-cost, mechanically compliant polymer interface between standard single mode(More)
As computing systems evolve for high performance with high power efficiency and exploit multi-core architecture, requirements for high-speed I/O are getting harder and could not be satisfied with optical interconnects. In addition to realize low power with optics by utilizing CMOS technology for high-sped driver circuits, chip-level packaging of optical(More)
In order to assess appropriate cooling solutions for three-dimensional (3D) chip stacks in various uses, it is important to have better understanding of the total thermal resistance of a 3D chip stack. For this purpose, precise thermal resistance measurements and modeling of each component of a 3D chip stack are important. A 3D chip stack is composed of(More)
We propose a new architecture of optical device integration on SLC carrier with capability of handling of the optical signals directly on MCM, or an optically enabled MCM, where VCSELs/PDs and the interface chips are placed closer to the main VLSI on a waveguide integrated SLC, while the optical connectors are at the periphery of the SLC carrier. This(More)
More optical channels have been implemented into computing systems as the system performance keeps increasing. Optical interconnects bring advantage of high data rate density, i.e. large bandwidth with small physical dimensions, as well as large bandwidth x distance product. High data rate density enables tight integration of many optical channels with(More)