Yogendra Joshi

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Power consumption and cooling overheads are becoming increasingly significant for large scale machines, affecting overall costs and the ability to extend resource capacities and performance capabilities. To help mitigate these issues, active power management technologies are being deployed aggressively, including power budgeting, which enables improved(More)
In this paper, we investigate the co-design of multicore architectures and microfluidic cooling for 3D stacked ICs. The architecture is a 16 core, x86 multicore die stacked with a second die hosting an L2 SRAM cache. First, a multicore x86 compatible cycle-level microarchitecture simulator was constructed and integrated with physical power models. The(More)
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