Yngvar Berg

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In this paper we present a new proposal for implementing a voltage-mode Multiple-Valued (MV) maximum or minimum function. The circuit has been implemented using Recharged Semi Floating-Gate (SFG) transistors. The benefit with this design is, the proposed circuits can easily be fabricated using a conventional CMOS process. The circuit is suitable for a low(More)
— This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with Recharged Semi-Floating Gate Devices. By using balanced ternary notation, it possible to take advantage of carry free addition, which is exploited in designing a fast adder cell. The circuit operates at 1 GHz clock frequency. The supply voltage is only 1.0 Volt. The(More)
This paper presents ternary counters using balanced ternary notation. The balanced ternary counters can replace binary full adders or counters in fast adder structures. The circuits use recharged CMOS semi-floating gate (RSFG) devices. By using balanced ternary notation, it is possible to build balanced ternary addition circuits, which can add both negative(More)
In this paper we present a novel voltage mode non-inverting CMOS Semi Floating-Gate(SFG) Ternary Switching Element. The design is applicable for reconstructing or refreshing ternary logic signals. The switching points are tuned using capacitive division. A preliminary simulation results from Cadence Spectre with AMS 0.35µmprocess parameters c35b4 is(More)
In this paper we investigate the relationship between the pulse-coded signal representation found in biological neurons and signals represented by first-order delta-sigma bit-streams. We show that a first-order delta-sigma bit-stream is a digital equivalent to a pulse-coded neural signal. By increasing the clock frequency, a delta-sigma bit-stream can(More)