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In this paper we examine the robustness and performance of static ultra low-voltage CMOS binary logic. The logic gates presented are designed using semi floating-gate transistors and resembles domino CMOS. The performance and robustness of different logic gates are examined and compared to complementary and domino CMOS logic.
— Ultra low-voltage (ULV) floating-gate (FG) differential amplifiers are presented. In this paper we present several different approaches to CMOS ULV amplifier design. Sinh-shaped and tanh-shaped transconductance amplifiers are described. Measured results are provided.
— An area efficient technique for tuning floating-gate circuits is described. The effective threshold voltage seen from a control gate can be programmed to virtually any value. The floating-gate transistor (FGMOS) may be used to implement low-power/low-voltage digital-and/or analog circuits.
— This paper describes a novel technique for implementing ultra low-voltage/low-power digital circuits. The effective threshold voltage seen from a control gate is adjusted during a UV-light activated tuning procedure. The optimal effective threshold voltage matching the supply voltage and speed may be programmed by UV-light through an activated conductance… (More)
— A programming technique for controlling the floating gates (FG) in ultra low-voltage (ULV) floating-gate circuits is presented. Simple ultra low-voltage floating-gate current scaling and level shifting circuits are discussed. The current scaling and level shifting are accomplished using only minimum sized transistors and floating capacitors. Floating-gate… (More)
In this paper we propose a novel technique for programming oating gate MOS transistors (FGMOS) in low-power design. By threshold-shifting low-power operation is possible with the cost of an extra polysilicon layer. Combining the FGMOS transistor with a UV-activated (UV) conduc-tance give rise to the UV-light programmable oating-gate MOS (FGUVMOS)… (More)
In this paper we present a new proposal for implementing a voltage-mode Multiple-Valued (MV) maximum or minimum function. The circuit has been implemented using Recharged Semi Floating-Gate (SFG) transistors. The benefit with this design is, the proposed circuits can easily be fabricated using a conventional CMOS process. The circuit is suitable for a low… (More)
— This article presents two new, reconfigurable multi-input floating-gate circuits able to produce either the INVERTED SUM / INVERTED CARRY functions for a FULL-ADDER, XNOR / NAND, or XOR / NOR. The circuits contain four MOSFETs and fourteen or nine capacitors, respectively. SPICE simulations are shown, demonstrating the principal operation, together with… (More)