In this paper we present a simple ultra low-voltage and high speed D flip-flop. The delay of the static differential flip-flop presented is less than 12% compared to conventional differential CMOS flip-flops. The presented circuits have been simulated using Hspice and are valid for 90nm TSMC CMOS process. The proposed high-speed and ultra low-voltage… (More)
In this paper we examine the robustness and performance of static ultra low-voltage CMOS binary logic. The logic gates presented are designed using semi floating-gate transistors and resembles domino CMOS. The performance and robustness of different logic gates are examined and compared to complementary and domino CMOS logic.
— Ultra low-voltage (ULV) floating-gate (FG) differential amplifiers are presented. In this paper we present several different approaches to CMOS ULV amplifier design. Sinh-shaped and tanh-shaped transconductance amplifiers are described. Measured results are provided.
— A programming technique for controlling the floating gates (FG) in ultra low-voltage (ULV) floating-gate circuits is presented. Simple ultra low-voltage floating-gate current scaling and level shifting circuits are discussed. The current scaling and level shifting are accomplished using only minimum sized transistors and floating capacitors. Floating-gate… (More)
— This paper describes a novel technique for implementing ultra low-voltage/low-power digital circuits. The effective threshold voltage seen from a control gate is adjusted during a UV-light activated tuning procedure. The optimal effective threshold voltage matching the supply voltage and speed may be programmed by UV-light through an activated conductance… (More)
— An area efficient technique for tuning floating-gate circuits is described. The effective threshold voltage seen from a control gate can be programmed to virtually any value. The floating-gate transistor (FGMOS) may be used to implement low-power/low-voltage digital-and/or analog circuits.
In this paper we present a new proposal for implementing a voltage-mode Multiple-Valued (MV) maximum or minimum function. The circuit has been implemented using Recharged Semi Floating-Gate (SFG) transistors. The benefit with this design is, the proposed circuits can easily be fabricated using a conventional CMOS process. The circuit is suitable for a low… (More)
— This paper presents a multiplier circuit using Balanced Ternary (BT) Notation. The multiplier can multiply both negative and positive numbers, which is one of the advantage able properties of the balanced ternary numbering systems. By using balanced ternary notation, it is possible to take advantage of carry free multiplication, which is exploited in… (More)