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—The explosive growth of 802.11-based wireless LANs has attracted interest in providing higher data rates and greater system capacities. Among the IEEE 802.11 standards, the 802.11a standard based on OFDM modulation scheme has been defined to address high-speed and large-system-capacity challenges. Hardware implementations are often used to meet the(More)
In this paper, we present a high performance Turbo CODEC implemented using digital signal processor for wireless systems following recommended CDMA2000 standard. At the transmitter side, the Turbo encoder is implemented with a modified 15×13 odd-even interleaver. As modern DSP chips, like TI C64x, are designed with multiple functional units, it is(More)
RSA is a popular cryptography algorithm widely used in signing and encrypting operations for security systems. Generally, the software implementations of RSA algorithm are based on 2-prime RSA. Recently multi-prime RSA has been proposed to speed up RSA implementations. Both 2-prime and multi-prime implementations require squaring reduction and(More)
Memory reference is one of the major courses of power consumption incurred in a microprocessor. In this paper, we propose two matrix transformation techniques to reduce the number of memory references in the FFT computation. With the first transformation, all the butterflies sharing the same twiddle factor will be clustered and computed together to(More)