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As network link rates are being pushed beyond 40Gbps, IP lookup in high-speed routers is moving to hardware. The TCAM (Ternary Content Addressable Memory)-based IP lookup engine and the SRAM (Static Random Access Memory)based IP lookup pipeline are the two most common way to achieve high throughput. However, route updates in both engines degrade lookup(More)
Programmable routers supporting virtualization are a key building block for bridging the gap between new Internet protocols and their deployment in real operational networks. This article presents the design and implementation of PEARL, a ProgrammablE virtuAl Router pLatform with relatively high-performance. It offers high flexibility by allowing users to(More)
Virtual routers are increasingly being studied, as an important building block to enable network virtualization. In a virtual router platform, multiple virtual router instances coexist, each having its own FIB (Forwarding Information Base). In this context, memory scalability and route updates are two major challenges. Existing approaches addressed one of(More)
Packet inspection is widely employed in application-layer protocol analyzing systems to enable accurate protocol identification. Many existing systems, however, fail to meet the requirement of keeping up with wire speed in networking. There are two limitations: (1) software-based matching schemes are usually in a sequential manner which is slow and(More)
Network virtualization which enables the coexistence of multiple networks in shared infrastructure adds extra requirements on data plane of router. Software based virtual data plane is inferior in performance, whereas, hardware based virtual data plane is hard to achieve flexibility and scalability. In this paper, using FPGA (Field Program Gate Array) and(More)
As the key building block for enabling network virtualization, virtual routers have attracted much attention recently. In a virtual router platform, multiple virtual router instances coexist, each with its own FIB (Forwarding Information Base). The small amount of high-speed memory in a physical router platform severely limits the number of FIBs supported,(More)
Packet replay is an important way to reproduce real traffic for network test. Many works focus on the performance and accuracy of packet generation based on hardware, such as NP and FPGA, in order to replace inefficient software based packet replay tools. However, limited onboard storage space constrains the size of trace file. In this paper, we design a(More)
An automatic, miniature and multi-parameter on-line water quality monitoring system based on a micro-spectrometer is designed and implemented. The system is integrated with the flow-batch analysis and spectrophotometric detection method. The effectiveness of the system is tested by measuring chemical oxygen demand (COD) and ammonia-nitrogen in water. The(More)
Parallel architecture has been used for packet processing of high speed links. Essential to such architecture is a load balancer which responsible for packet dispatching. In this paper, we design an embedded system for high speed OC192 network traffic load balancing. In the system, incoming traffic is load-balanced to 12 processing engines through Ethernet.(More)
Nowadays more and more small transistors make microprocessors more susceptible to transient faults, and then induce control-flow errors. Software-based signature monitoring is widely used for control-flow error detection. When previous signature monitoring techniques are applied to RISC architectures, there exist some branch-errors that they can not detect.(More)