Yingbiao Yao

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As the latest video coding standard, high efficiency video coding (HEVC) is a successor to H.264/AVC. To improve the coding efficiency of intra coding, HEVC employs a flexible quad-tree coding block partitioning structure and 35 intra prediction modes. The optimal prediction mode is selected through rough mode decision (RMD) and rate distortion optimisation(More)
This paper proposes general software optimization techniques for embedded systems based on processors, which mainly include general optimization methods in high language and software & hardware cooptimization in assembly language. Then these techniques are applied to optimize our MP3 decoder, which is based on RISC32, a RISC core compatible with MIPSI(More)
This paper presents an ISA model-based pseudorandom program generator, called as VirgoASM, for functional verification of RISC3200 processor. The kernel parts of VirgoASM are instruction generating models and test templates. In order to ensure the complete instruction generating space and the legality and validity of generated single instruction,(More)
Interference between primary user (PU) and secondary user (SU) transceivers should be mitigated in order to implement underlay spectrum sharing in cognitive radio networks (CRN). Considering this scenario, an improved joint subcarrier and bit allocation scheme for cognitive user with primary users’ cooperation (PU Coop) in CRN is proposed. In this scheme,(More)
This paper presents SimBuilder, a simulation system incorporating environmental and quality concerns into a traditional manufacturing simulation environment. These simulations can be used to generate a complete material balance around a particular manufacturing process and can be made available to design engineers to aid in life cycle design assessments. An(More)
With the rapid development of integrated circuit design technology and the processed tasks and data volumes growing, MPSoC is becoming increasingly popular in a variety of applications. In MPSoC design, parallelism is a very important issue, for example, how to realize task parallelism and data parallelism. Focusing on this issue, this paper analyzes the(More)
In order to derive the optimal on-chip memory architecture for a given application, the embedded system designer must spend considerable time evaluating potential memory designs. However, tight time-to-market constraints enforce short design cycle time. In this paper we present an effective method to fast and accurately estimate the on-chip data memory(More)
RISC-based processors have been extended into almost all kinds of embedded applications. These applications have different features thus require different processor architectures. Thus, we have developed a dual-core/dual-issue mixed micro-architecture processor named as RISC3202 which is based on two simple RISC cores. On the one hand, RISC3202 is an(More)