• Publications
  • Influence
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
TLDR
This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Expand
  • 827
  • 98
  • PDF
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
TLDR
We report a 10b SAR ADC that uses binary-scaled DAC networks for settling error compensation. Expand
  • 244
  • 19
  • PDF
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications
TLDR
This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. Expand
  • 111
  • 13
  • PDF
A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS
TLDR
This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. Expand
  • 56
  • 7
  • PDF
A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18µm CMOS
TLDR
This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. Expand
  • 103
  • 5
  • PDF
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
TLDR
This paper has proposed an algorithm for flip-flop replacement for power reduction in digital integrated circuit design. Expand
  • 62
  • 4
  • PDF
An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count
TLDR
This paper reports an asynchronous binary-search analog-to-digital converter (ADC) with reference range prediction that achieves the balance between power consumption and operation speed. Expand
  • 49
  • 4
  • PDF
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS
TLDR
This paper reports a 5b asynchronous binary-search ADC with reference-range prediction. Expand
  • 39
  • 4
  • PDF
A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS
TLDR
This paper presents a 4-way 1.6-GS/s time-interleaved (TI) SAR ADC with fast reference charge neutralization (CN) and background timing-skew calibration. Expand
  • 18
  • 4
10-bit 30-MS/s SAR ADC Using a Switchback Switching Method
TLDR
This brief presents a 10-bit 30-MS/s successive-approximation-register analog-to-digital converter (ADC) that uses a power efficient switchback switching method that reduces the power consumption and design effort of the reference buffer. Expand
  • 78
  • 3
  • PDF