Ying-Zu Lin

Publications
Influence

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

Chun-Cheng Liu, S. Chang, Guan-Ying Huang, Ying-Zu Lin
Physics, Computer Science
IEEE Journal of Solid-State Circuits
22 March 2010

This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Expand

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

Chun-Cheng Liu, S. Chang, +5 authors C. Tsai
Engineering, Computer Science
IEEE International Solid-State Circuits…
18 March 2010

We report a 10b SAR ADC that uses binary-scaled DAC networks for settling error compensation. Expand

A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications

Guan-Ying Huang, S. Chang, Chun-Cheng Liu, Ying-Zu Lin
Engineering, Computer Science
IEEE Journal of Solid-State Circuits
24 October 2012

This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. Expand

A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS

Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Y. Shyu, S. Chang
Physics
Symposium on VLSI Circuits
16 June 2010

This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. Expand

A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18µm CMOS

Chun-Cheng Liu, S. Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang
Engineering
Symposium on VLSI Circuits
16 June 2010

This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. Expand

Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops

Y. Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, S. Chang
Computer Science
IEEE Transactions on Very Large Scale Integration…
1 April 2013

This paper has proposed an algorithm for flip-flop replacement for power reduction in digital integrated circuit design. Expand

An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count

Ying-Zu Lin, S. Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang
Computer Science
IEEE Transactions on Circuits and Systems I…
1 August 2010

This paper reports an asynchronous binary-search analog-to-digital converter (ADC) with reference range prediction that achieves the balance between power consumption and operation speed. Expand

A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS

Ying-Zu Lin, S. Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang
Engineering, Computer Science
IEEE International Solid-State Circuits…
29 May 2009

This paper reports a 5b asynchronous binary-search ADC with reference-range prediction. Expand

A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS

Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Chao-Hsin Lu
Engineering, Computer Science
IEEE Symposium on VLSI Circuits (VLSI-Circuits)
15 June 2016

This paper presents a 4-way 1.6-GS/s time-interleaved (TI) SAR ADC with fast reference charge neutralization (CN) and background timing-skew calibration. Expand

10-bit 30-MS/s SAR ADC Using a Switchback Switching Method

Guan-Ying Huang, S. Chang, Chun-Cheng Liu, Ying-Zu Lin
Computer Science
IEEE Transactions on Very Large Scale Integration…
1 March 2013

This brief presents a 10-bit 30-MS/s successive-approximation-register analog-to-digital converter (ADC) that uses a power efficient switchback switching method that reduces the power consumption and design effort of the reference buffer. Expand

Recommended Authors