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A .~yste!ii I f i d d e s i p frrrliiework for FPCA-based DSP desigi~ is presented. The design pow ictilizes Sysfein Ceiiemfor, U svsfeni leoel fool developed by Xiliru, and 1i:il.s ir ro (I,I "ill-house'' archirerfurul synrhesis fool, IRIS. Wliilsf Svsfeiir Cellerafor allows FPCA-hosed Ii~fellect~tal Properq (IPJ cores fo be bicorporared info the desig,~(More)
—This paper presents a novel instruction cell-based re-configurable computing architecture for low-power applications, thereafter referred to as the reconfigurable instruction cell array (RICA). For the development of the RICA, a top-down software driven approach was taken and revealed as one of the key design decisions for a flexible, easy to program,(More)
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory architecture, and task mapping and scheduling. This paper presents an integer linear programming formulation for the task mapping and scheduling problem. The technique incorporates(More)
Increasing evidence reveals that diverse non-coding RNAs (ncRNAs) play critically important roles in viral infection. Viruses can use diverse ncRNAs to manipulate both cellular and viral gene expression to establish a host environment conducive to the completion of the viral life cycle. Many host cellular ncRNAs can also directly or indirectly influence(More)
We present a new De-Blocking Filter module fully optimised for use on a recently introduced dynamically reconfigurable, instruction cell based architecture. The module consists of a novel combination of standard software transforms alongside architecture specific techniques and aims to reduce reconfiguration overheads and increase utilisation of resources.(More)
As multiprocessor System-on-Chip (MPSoC) approaches become popular in embedded system designs, simulation tools for modelling these systems are highly in demand for evaluating the performance and cost at both hardware design stage and software development phase. This paper presents a fast, flexible, and cycle-accurate simulation tool for MPSoCs targeting(More)