Yifei Huang

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—We report a process for top-gate amorphous silicon thin-film transistors (α-Si TFTs) that employs a self-aligned metal silicide for source and drain (S/D). All process steps, including deposition of active layers and formation of metal silicide, are accomplished at temperatures that are less than or equal to 280 • C. The thermal budget is compatible with(More)
The recent financial crisis has brought to the forefront renewed concerns about the merit of financial development, especially for the most vulnerable segments of our population. Studies on the relationship between financial development and poverty have been inconclusive. Some claim that, by allowing more entrepreneurs to obtain financing, financial(More)
The overlap between the source/drain (S/D) electrode and the gate electrode in conventional bottom-gate amorphous silicon (a-Si) thin-film transistors (TFTs), typically several µm, results in parasitic capacitance that negatively impacts the power and speed performance of a-Si circuits. Devices with S/D self-aligned to the gate do not suffer from this(More)
Existing a-Si floating gate TFT (FG-TFT) nonvolatile memory suffers from two drawbacks: (i) short retention time [1] and (ii) strong dependence of drain saturation current (In , sAT) on drain voltage [2]. In this study, we present (i) a new device structure that eliminates In , sAT dependence on drain voltage; (ii) room­ temperature retention time of> 1 0(More)
—Transistors with floating gate, used for nonvolatile memory, have a saturation current that increases with drain voltage. This is the result of undesirable capacitive coupling between the floating gate and the drain electrode, which can occur in devices made on crystalline silicon or amorphous silicon (a-Si) technologies. In this paper, we report on a new(More)
While scaling VLSI devices to ever shrinking dimensions has driven much of the improvement in performance and reduction in cost of electronic intelligence, a new set of challenges and opportunities has emerged in a drastically different regime. As systems become more and more powerful, they are no longer limited by their electronic information processing(More)
—We have made self-aligned top-gate coplanar hydro-genated amorphous-silicon (a-Si:H) thin-film transistors using a SiO 2 –silicone hybrid material as the gate dielectric. The hybrid dielectric layer is 150 nm thick and separates a chromium gate electrode from nickel silicide source and drain. The nickel silicide is formed by rapid thermal reaction of a(More)
— An active-matrix organic light-emitting-diode (AMOLED) display which does not require pixel refresh is demonstrated. This was achieved by replacing the thin-film transistor (TFT) that drives the OLED with a non-volatile memory TFT, in a 2-transistor pixel circuit. The threshold voltage of the non-volatile-memory TFT can be changed by applying programming(More)
We develop a maximum penalized quasi-likelihood estimator for estimating in a non-parametric way the diffusion function of a diffusion process, as an alternative to more traditional kernel-based estimators. After developing a numerical scheme for computing the maximizer of the penalized maximum quasi-likelihood function, we study the asymptotic properties(More)
We have developed low-defect, low-stress plasma-enhanced chemical vapor deposition (PECVD) silicon nitride (SiN x) at 200°C. The intrinsic stress of this SiN x film is only-12.9 MPa (compressive). Coupled with the low defect (low charge trapping) characteristic of this low-stress SiN x , we are able to demonstrate amorphous silicon thin-film transistors(More)