Yi-Hsiang Chou

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Given an LB-compact floorplan, a 3D block-level thermal model is firstly proposed to calculate the temperature of each circuit block in reasonable time. Furthermore, based on the temperature calculation in the proposed 3D block-level thermal model and the final floorplan region, an iterative approach is proposed to reduce the final floorplan temperature by(More)
Given a 3D non-slicing floorplan, based on the property of packing-driven ordering in the floorplan, all the blocks can be ordered as a block list. Furthermore, according to the maintenance of a dynamic sliceable floorplan, any 3D non-slicing floorplan can be transformed into a 3D slicing floorplan by shifting the related blocks to minimize the final(More)
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