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Three-dimensional (3-D) integration promises continuous system-level functional scaling beyond the traditional 2-D device-level geometric scaling. It allows stacking memory dies on top of a logic die using through-silicon vias (TSVs) to realize high bandwidth by deploying the vertical connections between functional blocks. In this paper, we present a design(More)
In this paper, a low power and high performance three-dimensional (3-D) stacking multimedia platform called "3D-PAC" is proposed. This platform is a heterogeneous integration composed of a low power design logic layer (2D-PAC) and a reconfigurable memory tier via 3-D technology. After extensive 3-D architecture exploration with Electronic System Level (ESL)(More)
This paper proposes a novel method of remapping between any amount of individual systems or chips. Any individual system and chip can share a specific address map with other systems over the proposed adaptive memory map switch (AMMS). Because the AMMS is programmable, it allows the dynamic changing on the remapping of target address by setting AMMS. An(More)
The three-dimensional (3-D) stacking memory is good way to extend the local memory of embedded CPU and/or DSP by the through-silicon-vias (TSVs) technology. In this work, we show a multi-core system with 3-D stacking memory, and the stacking memory can be configured as instruction cache or local data memory for each DSP core. Due to the non-cacheable(More)
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