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In post-silicon debugging, low observability of internal signal values and large amount of traces are considered as the most critical problems. To address these problems, we propose an on-chip circuitry named DSC (Dynamic Slicing Circuit) which outputs the input signal values that actually influence on an erroneous output value in a particular execution of(More)
Post-silicon debugging efficiency is getting more critical to shorten the time-to-market than ever, as more bugs escape the verification in pre-silicon phase. Conventionally, simulation of corresponding low-level design description such as RTL or gate-level designs has been used to get observability and controllability. However, the simulation speed of such(More)
The development process of SoC is getting harder owing to the relentless rising complexity and time– to-market pressure. What is worse, the misunderstanding of specification due to the varied writing styles and gaps between each design level causes additional loss of time and cost. One of the most discussed methods to cope with this situation is design(More)
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