Yen-Lin Peng

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In this paper, we propose a new BIST-based approach for testing FPGA interconnect delay faults. The BIST architecture utilizes the regularity of an FPGA by implementing small test circuits repetitively over FPGA's CLB arrays. Each test circuit targets a specific path and determine conformance of the path delay according to a test clock. With the target path(More)
A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our fault model assumes that a target segment can be covered by a shortest path which is realizable in an FPGA, and the path will guarantee to detect delay defects which affect the performance of the segment. Given the proposed fault model, we also developed a framework to(More)
Testing for performance problems of FPGAs has become an important task for ever-increasingly advanced technology. To develop effective testing methodologies, a tool to independently evaluate the quality of test configurations is therefore much needed. In this paper, we present a method to calculate coverages of randomly distributed multiple delay defects in(More)
3-D integration has been touted as an approach to reducing the lengths of critical paths in field-programmable gate arrays (FPGAs). A 3-D chip stacks a number of 2-D FPGA bare dies, interconnected by through-silicon vias (TSVs) and micro bumps, to attain a high packing density. However, the technology also introduces new types of defects, such as TSV void(More)
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