Yen-Liang Yeh

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In this paper, we present design and analysis of a <i>W</i>-band divide-by-three injection-locked frequency divider (ILFD) in 90 nm CMOS process. Based on the proposed topology, the locking range can be enhanced without additional dc power consumption due to the boost of the second harmonic in the ILFD, and the small input capacitance is more feasible for(More)
In this paper, we present design and analysis of an innovative low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked phase-locked loop (PLL) with self-aligned delay-locked loop in 65-nm CMOS technology. With the proposed innovative topology, the phase between the injection signal and the voltage-controlled oscillator in the PLL can be(More)
A <i>W</i>-band wide locking range injection-locked frequency tripler (ILFT) with low dc power consumption is presented in this paper. By using a transformer coupled (TC) topology, the proposed TC-ILFT features the following advantages: 1) the negative resistance of the cross-coupled pair is not degraded due to the proposed TC-ILFT without source(More)
A Ka-band monolithic high-efficiency frequency quadrupler using a GaAs heterojunction bipolar transistor and pseudomorphic high electron-mobility transistor technology is presented in this paper. The frequency quadrupler is constructed cascading two frequency doublers. The frequency doubler employs a modified common-base/common-source topology to enhance(More)
A 2.2-2.4 GHz self-aligned sub-harmonically injection-locked phase-locked loop (PLL) using 65 nm CMOS process is presented in this paper. A delay-locked loop is employed in the proposed PLL to automatically align the phase difference between the injection signal and the sub-harmonically injection-locked voltage controlled oscillator. At 2.3 GHz, the(More)
In this paper, we present design and analysis of a K-band (18 to 26.5 GHz) low-phase-noise phase-locked loop (PLL) with the subharmonically injection-locked (SIL) technique. The phase noise of the PLL with subharmonic injection is investigated, and a modified phase noise model of the PLL with SIL technique is proposed. The theoretical calculations agree(More)
Design and analysis of low-phase-noise low-jitter subharmonically injection-locked voltage-controlled oscillator (VCO) with frequency-locked loop (FLL) self-alignment technique is presented in this paper using 90-nm CMOS process. The issue of the narrow locking range for the subharmonically injection-locked VCO (SILVCO) can be resolved over the variations,(More)
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