Yean-Yow Hwang

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The intellectual property @) business model is ~erable to a number of potentirdly devastating obstructions, such as misapprop-riation and intellwtu~ property fraud. We propose anew method for ~ protection @P) which facilitates design watermarking at the combinationrd logic synthesis level. We developd protocols for embedding designer-antior tool-spmific(More)
In this paper, we present an improvement of the FlowMap algorithm, named CutMap, which combines depth and area minimization during the mapping process by computing min-cost min-height K-feasible cuts for critical nodes for depth minimization and computing min-cost K-feasible cuts for non-critical nodes for area minimization. CutMap guarantees depth-optimal(More)
In this paper, we developed Boolean matching techniques for complex programmable logic blocks (PLBs) in LUT-based FPGAs. A complex PLB can not only be used as a <italic>K</italic>-input LUT, but also can implement some wide functions of more than <italic>K</italic> variables. We apply previous and develop new functional decomposition methods to match wide(More)
—Recently, design reuse has emerged as a dominant design and system-integration paradigm for modern systems on silicon. However, the intellectual-property-business model is vulnerable to many dangerous obstructions, such as misappro-priation and copyright fraud. The authors propose a new method for intellectual-property protection that relies upon design(More)
In this paper, we study the problem of decomposing gates in fanin-unbounded or K-bounded networks such that the K-input LUT mapping solutions computed by a depth-optimal mapper have minimum depth. We show (1) any decomposition leads to a smaller or equal mapping depth regardless the decomposition algorithm used, and (2) the problem is NP-hard for unbounded(More)
In this paper, we give a necessary and sufficient condition for the existence of partially-dependent functional decomposition and develop new algorithms to compute such decompositions. We apply our method to the synthesis and mapping for Xilinx XC4000 FPGA's which contain non-uniform sizes of LUT's in its architecture. We develop a new mapping algorithm(More)
In this paper we study structural gate decomposition in general, simple gate networks for depth-optimal technology mapping using <italic>K</italic>-input Lookup-Tables (<italic>K</italic>-LUTs). We show that (1) structural gate decomposition in any <italic>K</italic>-bounded network results in an optimal mapping depth smaller than or equal to that of the(More)
In this paper we study the technology mapping problem for FPGAs with nonuniform pin delays and fast interconnections. We develop the PinMap algorithm to compute the delay optimal mapping solution for FPGAs with nonuniform pin delays in polynomial time based on the eecient cut enumeration. Compared with FlowMap 5] without considering the nonuniform pin(More)
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