Yasuto Kuroda

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An 18-Mb full ternary CAM with low-voltage matchline sensing scheme (LVMLSS) is designed and fabricated in 65-nm bulk CMOS process. LVMLSS has three key techniques: voltage down converter, differential sense amplifier with matchline isolation, and reference voltage generation scheme. With these techniques, LVMLSS can reduce the dynamic power consumption of(More)
Ternary content addressable memory (TCAM) is popular LSI for use in high-throughput forwarding engines on routers. However, the unique structure applied in TCAM consume huge amounts of power, therefore it restricts the applicability to deployment for handling large lookup-table capacity in IP routers. In this paper, we propose a commodity-memory based(More)
Recently, energy consumption of routers has become a serious problem, hence power reduction is an urgent and important challenge. Existing routers always work 100% of their potentials regardless of required performance, such as volume of input traffic. However, semiconductor devices such as lookup logics, buffers, fabrics are not always fully utilized. In(More)
Packet classification has become increasingly complex and important to network equipment intended for future use. A recent trend to achieve complex packet classification is to use software-based methods, which tend to be slower than hardware-based methods. For search, this typically means using ternary content-addressable memory (TCAM) to make(More)
Wire-rate packet processing and its energy saving for over 100 Gbps speed of line are the issues to resolve in optical packet switching. For that purpose, we have newly developed an electronic header processing unit for optical packets in which the 23-bit longest prefix matching (LPM) forwarding engine LSIs are embedded. This paper reports the successful(More)