Yasuo Unekawa

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An 802.11a compliant medium access control (MAC) and physical layer (PHY) processing chip has been successfully fabricated in 0.18m CMOS. Thirty million transistors are integrated on a 10 91 10 91 mm die housed in a 361-pin PFBGA. The MAC functions are fully implemented by firmware on an embedded 32-b RISC processor, 4-Mb SRAM, and hardware acceleration(More)
This paper presents a simple data rate choosing method for multi data rate communication systems. This method is based on Viterbi decoding and aims to utilize relative likelihood between selected and unselected paths in the decoding. We confirmed the validity of our proposed method with computer simulations. The physical layer specifications are following(More)