Yasuo Hidaka

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Next-generation communication standards, such as OIF-CEI-25G-LR and IEEE P802.3bj, demand high-speed electrical backplane transceivers that support data rates around 25Gb/s. For such data rates and beyond, transmitter design becomes a significant technical challenge because a transmitter is the most bandwidth-hungry circuit that requires the highest clock(More)
A low-power pre-emphasis voltage mode transmitter architecture with output swing control, pre-emphasis coefficient control, and online impedance calibration is proposed and demonstrated. A 65nm LP CMOS implementation of this architecture dissipates only ~10mW from a 1.2V supply when transmitting 10Gb/s 400mV differential peak-to-peak data with 2-tap(More)