Yasuhiro Nara

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  • Yasuhiro Nara
  • 2009 International Symposium on VLSI Technology…
  • 2009
Scaling challenges for MOSFET fabrication process with design rule of 32nm and below will be reviewed. This paper will especially focus on the scaling issues of conventional planar bulk CMOS technology and discuss about multiple stress engineering, junction engineering and high-k/metal gate stack as key technology boosters to enhance CMOS performance with(More)
A high-speed continuous-system simulator of the multi-microprocessor configuration will be presented. This system is composed of simple microprocessor units and carries out highly parallel operations on a small task level. The processor unit is controlled by the microprogram and only performs basic operations such as integration, addition, and(More)
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