Yasir Hashim

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  • Yasir Hashim
  • 2016
This This paper is to suggest a new model for predicting the static characteristics of nanowire-CMOS (NW-CMOS) inverter. This model depends on experimental (or simulated) output characteristics of load and driver transistors separately as an input data. This model used in this research to investigate the effect of length (L), oxide thickness (Tox) and(More)
This paper represents diameter and logic voltage level optimizations of 6-Silicon Nanowire Transistors (SiNWT) SRAM. This study is to demonstrate diameter of nanowires effects at a different logic voltage level (Vdd) on the static characteristics of Nano-scale SiNWT Based SRAM Cell. Noise margins (NM) and inflection voltage (Vinf) of transfer(More)
This paper highlights an effort to study the characteristics of silicon CMOS nanowire transistor and the effect of cross-sectional area of PMOS transistor on silicon nanowire-CMOS inverter characteristics. In this study generated MATLAB code is used together with NanoHub MuGFET simulation tool to produce the characteristics of silicon nanowire transistors(More)
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