Yasir Hashim

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This paper presents the temperature characteristics of silicon nanowire transistors (SiNWTs) and examines the effect of temperature on transfer characteristics, threshold voltage, I(ON)/I(OFF) ratio, drain-induced barrier lowering (DIBL), and sub-threshold swing (SS). The (MuGFET) simulation tool was used to investigate the temperature characteristics of a(More)
This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this(More)
  • Yasir Hashim
  • 2016 International Conference On Advanced…
  • 2016
This This paper is to suggest a new model for predicting the static characteristics of nanowire-CMOS (NW-CMOS) inverter. This model depends on experimental (or simulated) output characteristics of load and driver transistors separately as an input data. This model used in this research to investigate the effect of length (L), oxide thickness (Tox) and(More)
This paper represents the temperature characteristics of silicon nanowire transistor of rectangular cross-section, temperature effect on transfer characteristics, I<sub>ON</sub>/1<sub>oFF</sub> ratio and sub-threshuld swing was studied. OMEN nanowire simulation tool was used to investigate temperature characteristics of transistor with three types of(More)
This study is the first to demonstrate characteristics optimization of nanowire resistance load inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on resistance value. Increasing of load resistor tends to increasing in noise margins until(More)
This study is the first to demonstrate dimensional optimization of nanowire-complementary metal-oxide-semiconductor inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both dimensions ratio and digital voltage level (Vdd). Diameter(More)
This paper represents diameter and logic voltage level optimizations of 6-Silicon Nanowire Transistors (SiNWT) SRAM. This study is to demonstrate diameter of nanowires effects at a different logic voltage level (Vdd) on the static characteristics of Nano-scale SiNWT Based SRAM Cell. Noise margins (NM) and inflection voltage (Vinf) of transfer(More)
This paper highlights an effort to study the characteristics of silicon CMOS nanowire transistor and the effect of cross-sectional area of PMOS transistor on silicon nanowire-CMOS inverter characteristics. In this study generated MATLAB code is used together with NanoHub MuGFET simulation tool to produce the characteristics of silicon nanowire transistors(More)
This paper shows the effect of the dimensions of nanowires on threshold voltage, ON/OFF current ratio, and sub-threshold slope. These parameters are critical factors of the characteristics of silicon nanowire transistors. The MuGFET simulation tool was used to investigate the characteristics of a transistor. Current-voltage characteristics with different(More)
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