Yao-Jung Yeh

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This paper presents a novel algorithm for field programmable gate array (FPGA) realization of vector quantizer (VQ) encoders using partial distance search (PDS). In most applications, the PDS is adopted as a software approach for attaining moderate codeword search acceleration. In this paper, a novel PDS algorithm well suited for hardware realization is(More)
This paper presents a novel low-cost and high-performance VLSI architecture for fuzzy c-means clustering. In the architecture, the operations at both the centroid and data levels are pipelined to attain high computational speed while consuming low hardware resources. In addition, the usual iterative operations for updating the membership matrix and cluster(More)
This paper presents a novel architecture for k-nearest neighbor (kNN) classification using field programmable gate array (FPGA). In the architecture, the first k closest vectors in the design set of a kNN classifier for each input vector are first identified by performing the partial distance search (PDS) in the wavelet domain. To implement the PDS in(More)
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