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Improving the hardware efficiency of video coding LSI like MPEG-4/H.264 is a recent design trend in implementing multi-media systems aimed at high-throughput design for high definition (HD) video [1] and low-power design for portable video [2]. However, it is difficult to trade-off power consumption and video quality like programmable processors do for(More)
In this paper we present a high throughput VLSI architecture design for Context-based Adaptive Binary Arithmetic Decoding (CABAD) in MPEG-4 AVC/H.264. To speed-up the inherent sequential operations in CABAD, we break down the processing bottleneck by proposing a look-ahead codeword parsing technique on the segmenting context tables with cache registers,(More)
This paper proposes a dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width. A design automation environment for simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 um CMOS technology, it comprises 439Kgates/10.9KB SRAM(More)
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