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—N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. Drive current for typical devices is found to be(More)
A silicon nanowire-FET (SiNAWI-FET) for high performance logic device with consideration of current direction effects and terabit non-volatile memory (NVM) device using an 8nm SiNAWI-NVM with oxide/nitride/oxide (ONO) and omega-gate structure is reported for the first time. N-and P-channel SiNAWI-FET showed the highest driving current on (110)/<110> crystal(More)
  • Yang-Kyu Choi, Kazuya Asano, Nick Lindert, Vivek Subramanian, Tsu-Jae King, Jeffrey Bokor +1 other
  • 2000
—A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with 5 nm UTB. A raised poly-Si S/D(More)
  • Xuejue Huang, Wen-Chin Lee, Charles Kuo, Digh Hisamoto, Leland Chang, Jakub Kedzierski +8 others
  • 1999
High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. 45 nm gate-length PMOS FinFET has an I dsat of 410 2A/2m (or 820 2A/2m depending on the definition of the width of a double-gate device) at Vd = Vg = 1.2 V and Tox = 2.5 nm. The(More)
  • Xuejue Huang, Wen-Chin Lee, Charles Kuo, Digh Hisamoto, Leland Chang, Jakub Kedzierski +8 others
  • 2001
—High-performance PMOSFETs with sub-50–nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides(More)
A novel microelectrode modification method is reported for neural electrode engineering with a flake nanostructure (nanoflake). The nanoflake-modified electrodes are fabricated by combining conventional lithography and electrochemical deposition to implement a microelectrode array (MEA) on a glass substrate. The unique geometrical properties of nanoflake(More)
—Nanoscale ultrathin body (UTB) p-channel MOS-FETs with body thickness down to 4 nm and raised source and drain (S/D) using selectively deposited Ge are demonstrated for the first time. Devices with gate length down to 30 nm show high drive current, low off current, and excellent short-channel behavior. Mobility enhancement and threshold-voltage shift due(More)
The levels of aspartate aminotransferase (AST/GOT) and alanine aminotransferase (ALT/GPT) in serum can help people diagnose body tissues especially the heart and the liver are injured or not. This article provides a comprehensive review of research activities that concentrate on AST/GOT and ALT/GPT detection techniques due to their clinical importance. The(More)
—Resistive switching characteristics are investigated for Al/TiO x /Al devices, particularly for the structural effects in crossbar and via-hole-type devices. The via-hole structure shows more reliable switching characteristics than the crossbar structure, owing to the elimination of possible edge effects. The asymmetric switching behavior is analyzed with(More)
—The hydrogen annealing process has been used to improve surface roughness of Si-fin in CMOS FinFETs for the first time. The hydrogen annealing was performed after Si-fin etch and before gate oxidation. As a result, increased saturation current with a lowered threshold voltage and a decreased low-frequency noise level over the entire range of drain current(More)