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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
TLDR
A 1.2 V 10-bit 100 MS/s Successive Approximation ADC achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Expand
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A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure
TLDR
An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. Expand
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Split-SAR ADCs: Improved Linearity With Power and Speed Optimization
  • Yan Zhu, C. Chan, +4 authors F. Maloberti
  • Computer Science, Mathematics
  • IEEE Transactions on Very Large Scale Integration…
  • 1 February 2014
TLDR
This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. Expand
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An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS
TLDR
This paper presents an 11 bit 450 MS/s three-way time-interleaved (TI) subranging pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) that achieves a high conversion rate and accuracy with good power efficiency. Expand
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A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation
TLDR
This paper presents a time-interleaved pipelined-SAR ADC with on-chip offset cancellation technique. Expand
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A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS
TLDR
This paper presents a reconfigurable, low offset, low noise and high speed dynamic clocked-comparator for medium to high resolution Analog to Digital Converters (ADCs). Expand
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26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS
TLDR
This paper presents a combination of 4× time interleaving and 3b/cycle multi-bit SAR ADC in 65nm CMOS, achieving a Nyquist FoM of 39fJ/conv-step for 5GS/s at 1V supply. Expand
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A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC
TLDR
This paper presents a 4× time-interleaved 6-bit 5 GS/s 3 b/cycle SAR analog-to-digital converter (ADC). Expand
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A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC
TLDR
A 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC architecture is proposed, where the ADC's front-end is built with a 5b binary search ADC, shared by two time-Interleaved 6b SAR ADCs in the 2nd-stage. Expand
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A power-efficient capacitor structure for high-speed charge recycling SAR ADCs
TLDR
A novel capacitor array structure for a charge recycling capacitive DAC has been proposed which can be applied to high-speed SAR ADCs. Expand
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