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Distributed Memory Management Units Architecture for NoC-based CMPs
TLDR
We propose a novel distributed MMU architecture for NoC-based CMPs, which can effectively reduce the bottleneck effect in contrast of traditional MMU. Expand
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A Power-aware Hybrid Storage Architecture for Ubiquitous Computing ?
As the media functions of pervasive computer systems are getting more powerful and popular, many pervasive applications need large capacity of storage. Meantime, power consumption is a signiflcantExpand
The changing nature of Spam 2.0
TLDR
The paper contributes in this direction by attempting to understand the root cause of the problem, by investigating the changing nature of Spam 2.0 and using the collected data to identify trends within the spam corpus. Expand
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Hardware Thread Accelerating Method based on CPU/FPGA Hybrid Architecture
TLDR
The CPU/FPGA hybrid architecture is a popular reconfigurable computing architecture. Expand
PZSPTF: Parallelism-aware and Zone-based Shortest Positioning TimeFirst Scheduling for MEMS-based Storage Devices
TLDR
A new request scheduling algorithm is explored for MEMS-based storage devices in this paper, which is named parallelism-aware and zone-based shortest positioning time first (PZSPTF). Expand