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The emergence of large-scale chip multicore processors makes the on-chip parallel H.264/AVC encoder with high parallelism feasible. To reduce the data reload frequency, a hierarchical chip multi-core DSP platform with overall 64 DSP cores is designed to accommodate the computation/data-intensive H.264/AVC encoder. To increase parallelism, macro block level(More)
Single-core DSP becomes more and more difficult to meet the demand of some application-specific fields, such as 3G mobile communication, consumer electronic systems and intelligent control devices. Recently, Multi-core DSP has received much concern and is believed to be an effective method to improve performance. QDSP is a multi-core DSP SoC developed by(More)
System-on-Chip(SoC) designs become more complex nowadays. The communication between processing elements are suffering challenges due to the wiring problem. Networks-on-Chip(NoC) approach was proposed as a promising solution. Buffers are one of the major resources used by the routers. In this paper, an application-specific buffer planning approach that can(More)
To minimize the delay of the data communication, hierarchical On-chip Large-scale Parallel Computing architectures (OLPCs) with communication locality awareness are recently studied by researchers. This paper proposes a hierarchical architecture consisting of SMP clustered nodes, each of which is structured by more than one baseline cores through(More)
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