Yael Abarbanel

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Intel's move towards the SoC paradigm comes with a compelling requirement for shorter time-to-market. To address that, we need to make both pre and post silicon validation more efficient. In this paper we focus on post-si functional validation, which consumes an increasing share of the overall product development timeline. We present a coherent Pre-to-Post(More)
In SoC, key infrastructure/backbone flows are distributed across many IPs and involve tight firmware and hardware interaction. Examples include resets, power management, security, and more. Traditional hardware validation techniques are no-longer adequate for such flows, due to the short time-to-market requirements, in particular, for mobile devices. In(More)
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