Y. Shyu

Publications
Influence

A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS

Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Y. Shyu, S. Chang
Physics
Symposium on VLSI Circuits
16 June 2010

This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. Expand

Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops

Y. Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, S. Chang
Computer Science
IEEE Transactions on Very Large Scale Integration…
1 April 2013

This paper has proposed an algorithm for flip-flop replacement for power reduction in digital integrated circuit design. Expand

A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS

Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Y. Shyu, Yen-Ting Liu, S. Chang
Physics, Computer Science
IEEE Transactions on Circuits and Systems I…
11 February 2013

This paper presents a 9-bit subrange analog-to-digital converter (ADC) consisting of a 3.5-bit flash coarse ADC, a 6-bit successive-approximation-register (SAR) fine ADC, and a differential segmented capacitive digital- to-analog converter (DAC). Expand

A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS

Ying-Zu Lin, S. Chang, Y. Shyu, Guan-Ying Huang, Chun-Cheng Liu
Physics, Computer Science
IEEE Asian Solid-State Circuits Conference
1 November 2011

This paper presents a new subrange analog-to-digital converter (ADC): a binary-search coarse ADC + a SAR fine ADC that improves conversion speed and gives coarse capacitors longer settling time. Expand

A Systematic Design Methodology of Asynchronous SAR ADCs

Chun-Po Huang, Jai-Ming Lin, Y. Shyu, S. Chang
Computer Science
IEEE Transactions on Very Large Scale Integration…
1 May 2016

This paper presents a systematic sizing procedure and a sizing tool for asynchronous SAR ADCs based on design considerations. Expand

A bias-driven approach for automated design of operational amplifiers

Cheng-Wu Lin, Pin-Dai Sue, Y. Shyu, S. Chang
Computer Science
International Symposium on VLSI Design…
28 April 2009

This paper presents a transistor-level automation to perform component sizing, power optimization and layout generation for fully-differential operational amplifiers (op-amps). Expand

A 12-b 40-MS/s Calibration-Free SAR ADC

Chung-Wei Hsu, S. Chang, +6 authors Huan-Jui Hu
Computer Science
IEEE Transactions on Circuits and Systems I…
1 March 2018

This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). Expand

A pipeline ADC with latched-based ring amplifiers

Wen-Tze Chen, Y. Shyu, Chun-Po Huang, S. Chang
Engineering, Computer Science
IEEE International Symposium on Circuits and…
22 May 2016

This paper presents a latched-based ring amplifier which is capable of decreasing the probability of oscillation. Expand

A Primary-Auxiliary Temperature Sensing Scheme for Multiple Hotspots in System-on-a-Chips

Peng-Yu Chen, Guan-Ying Huang, Y. Shyu, S. Chang
Engineering
IEEE Sensors Journal
1 April 2014

A primary-auxiliary temperature sensing scheme for system-on-a-chip application is proposed in this paper. Taking advantage of the high accuracy and linearity of the analog primary temperature… Expand

A systematic design automation approach for flash ADCs

Chun-Po Huang, Yin-Zu Lin, Cheng-Wu Lin, Y. Shyu, S. Chang
Computer Science
International Symposium on Next Generation…
17 December 2010

This paper presents a simulation-based top-down systematic design procedure for flash ADCs that provides a fast and easy way to design a flash ADC without related experiences. Expand

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