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A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS
TLDR
This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. Expand
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Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
TLDR
This paper has proposed an algorithm for flip-flop replacement for power reduction in digital integrated circuit design. Expand
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A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS
TLDR
This paper presents a 9-bit subrange analog-to-digital converter (ADC) consisting of a 3.5-bit flash coarse ADC, a 6-bit successive-approximation-register (SAR) fine ADC, and a differential segmented capacitive digital- to-analog converter (DAC). Expand
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A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS
TLDR
This paper presents a new subrange analog-to-digital converter (ADC): a binary-search coarse ADC + a SAR fine ADC that improves conversion speed and gives coarse capacitors longer settling time. Expand
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A Systematic Design Methodology of Asynchronous SAR ADCs
TLDR
This paper presents a systematic sizing procedure and a sizing tool for asynchronous SAR ADCs based on design considerations. Expand
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A bias-driven approach for automated design of operational amplifiers
TLDR
This paper presents a transistor-level automation to perform component sizing, power optimization and layout generation for fully-differential operational amplifiers (op-amps). Expand
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A 12-b 40-MS/s Calibration-Free SAR ADC
TLDR
This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). Expand
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A pipeline ADC with latched-based ring amplifiers
TLDR
This paper presents a latched-based ring amplifier which is capable of decreasing the probability of oscillation. Expand
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A Primary-Auxiliary Temperature Sensing Scheme for Multiple Hotspots in System-on-a-Chips
A primary-auxiliary temperature sensing scheme for system-on-a-chip application is proposed in this paper. Taking advantage of the high accuracy and linearity of the analog primary temperatureExpand
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A systematic design automation approach for flash ADCs
TLDR
This paper presents a simulation-based top-down systematic design procedure for flash ADCs that provides a fast and easy way to design a flash ADC without related experiences. Expand
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