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Power conscious fixed priority scheduling for hard real-time systems
Power efficient design of real-time systems based on programmable processors becomes more important as system functionality is increasingly realized through software. This paper presents a powerExpand
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Power optimization of real-time embedded systems on variable speed processors
TLDR
We propose a power optimization method for real-time embedded applications on a VSP with a power-down mode. Expand
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Architecting voltage islands in core-based system-on-a-chip designs
TLDR
We define the problem of architecting voltage islands in core-based designs and present a new algorithm for simultaneous voltage island partitioning, voltage level assignment and physical-level floorplanning. Expand
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Power conscious fixed priority scheduling for hard real-time systems
TLDR
This paper presents a power efficient version of a widely used fixed priority scheduling method by exploiting slack times, both those inherent in the system schedule and those arising from variations of execution times. Expand
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Partial bus-invert coding for power optimization of system level bus
TLDR
We presen t a partial bus-in vertcoding scheme for po wer optim ization of system level bus. Expand
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Power distribution analysis of VLSI interconnects using model orderreduction
  • Y. Shin, T. Sakurai
  • Engineering, Computer Science
  • IEEE Trans. Comput. Aided Des. Integr. Circuits…
  • 7 August 2002
TLDR
The analysis and simulation of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. Expand
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Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications
  • Hyung-Ock Kim, Y. Shin
  • Engineering, Computer Science
  • IEEE Transactions on Circuits and Systems II…
  • 18 June 2007
TLDR
The application of power gating to cell-based semi- custom design typically calls for customized cell libraries, which incurs substantial engineering efforts. Expand
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Coupling-driven bus design for low-power application-specific systems
TLDR
We address a bus ordering problem for low-power application-specific systems. Expand
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Pulsed-Latch Circuits: A New Dimension in ASIC Design
TLDR
Pulsed-latch circuits retain the advantages of both latches and flip-flops, offering higher performance and lower power consumption within a conventional ASIC design environment. Expand
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Partial bus-invert coding for power optimization of system level bus
We present a partial bus-invert coding scheme for power optimization of system level bus. In the proposed scheme, we select a sub-group of bus lines involved in bus encoding to avoid unnecessaryExpand
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