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A CMOS charge pump for low voltage operation
TLDR
This paper proposes a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. Expand
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Differential CMOS edge-triggered flip-flop based on clock racing
A differential CMOS edge-triggered flip-flop is proposed that employs a pair of cross-coupled inverters, providing fully static operation. The edge-triggering operation is achieved by a narrow pulse,Expand
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Fast 1V bootstrapped inverter suitable for standard CMOS technologies
The authors propose a novel low-voltage bootstrapped inverter, designed in a standard high VT 0.35µm CMOS technology. To enhance the switching speed of a CMOS inverter at low-voltage operation, anExpand
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High performance level restoration circuits for low-power reduced-swing interconnect schemes
TLDR
Two high performance level restoration circuits are proposed, suitable for high performance low-swing interconnect schemes. Expand
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Realistic end-to-end simulation of the optoelectronic links and comparison with the electrical interconnections for system-on-chip applications
A detailed comparison of optoelectronic versus electrical interconnections for system-on-chip applications is performed in terms of signal latency and power consumption. Realistic end-to-end modelsExpand
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Comparative study of different current mode sense amplifiers in submicron CMOS technology
A comparison of different current mode sense amplifiers using 0.25 /spl mu/m CMOS technology is presented. The sense amplifiers under consideration are suitable for current sensing in SRAM and flashExpand
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Charge Pump Circuits for Low-voltage Applications
TLDR
In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed, based on cascading several crossconnected NMOS voltage doubler stages. Expand
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Dynamic back bias CMOS driver for low-voltage applications
A high performance CMOS driver scheme for low-voltage applications is proposed. The threshold voltage of the MOS devices is electrically controlled in order to achieve high-speed operation during theExpand
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Comparison of the signal latency in optical and electrical interconnections for interchip links
TLDR
Substitution of electrical links by their optoelectronics counterparts has been regularly debated for more than a decade. Expand
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A CMOS differential logic for low-power and high-speed applications
TLDR
A new logic family called Charge-sharing at precharge differential logic (CSPDL) is proposed. Expand
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