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A novel BEOL transistor (BETr) with InGaZnO embedded in Cu-interconnects for on-chip high voltage I/Os in standard CMOS LSIs
A novel BEOL transistor (BETr) is developed in Cu interconnects with wide band-gap InGaZnO (IGZO) film for on-chip high voltage I/Os in standard CMOS LSIs only by one additional mask. Underlying Cu
A Novel Variable Inductor Using a Bridge Circuit and Its Application to a 5–20 GHz Tunable LC-VCO
TLDR
A novel variable inductor using a bridge circuit is proposed, which is suit able for the clock generation of high-speed communication systems, multi-core processors, as well as low-power, low-cost wireless transceivers.
A 60 ns 1 Mb nonvolatile ferroelectric memory with non-driven cell plate line write/read scheme
TLDR
A non-driven cell plate line write/read scheme (NDP scheme) is presented which leads to NVFRAMs with as fast access time as DRAMs.
Highly reliable BEOL-transistor with oxygen-controlled InGaZnO and Gate/Drain offset design for high/low voltage bridging I/O operations
Reliability of BEOL-transistors with a wide-gap oxide semiconductor InGaZnO (IGZO) film, integrated on LSI Cu-interconnects, is intensively discussed in terms of application to on-chip bridging I/Os
High on/off-ratio P-type oxide-based transistors integrated onto Cu-interconnects for on-chip high/low voltage-bridging BEOL-CMOS I/Os
A new P-type amorphous SnO thin-film transistor with high I<sub>on</sub>/I<sub>off</sub> ratio of >10<sup>4</sup> is developed, for the first time, as a component to complement N-type IGZO
Chemical Structure Effects of Ring-Type Siloxane Precursors on Properties of Plasma-Polymerized Porous SiOCH Films
Physical and chemical properties of plasma-polymerized SiOCH films were investigated using ring-type siloxane monomers with several kinds of side-chain chemicals, and a design principle of the
Interconnect design strategy: structures, repeaters and materials toward 0.1 /spl mu/m ULSIs with a giga-hertz clock operation
With the interconnect analysis using the LSI performance prediction model, the local and global line structures are optimized from 0.18 to 0.1 /spl mu/m generations. The chip size enlargement with
Crosstalk Analysis Method of 3-D Solenoid On-chip Inductors for High-speed CMOS SoCs
A crosstalk between miniaturized "3-D solenoid" on-chip inductors with multi-layered local interconnects is analyzed by an equivalent circuit model using the mixed-mode S-parameters. The circuit
High tolerance operation of 1T/2C FeRAMs for the variation of cell capacitors characteristics
The operation of an FeRAM test chip is demonstrated with an 8 kbit cell array, sense amplifiers and other peripheral circuits for confirming the high tolerance of the 1T/2C FeRAM. The test chip is
A novel cylinder-type MIM capacitor in porous low-k film (CAPL) for embedded DRAM with advanced CMOS logics
A novel cylinder-type metal-insulator-metal (MIM) capacitor in porous low-k film (CAPL) is proposed for embedded DRAMs (eDRAMs). The CAPL removes long bypass-contacts (BCT) with high resistance,
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