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This paper deals with the implementation of globally asynchronous locally synchronous (GALS), micropipelined processor in field programmable gate arrays (FPGA). Associated issues like delay model incorporating on-chip, technology independent single inverter ring oscillator (SIRO) and an unbundled datapath based on bit-encoding and return-to-zero (RTZ)(More)
A Single Inverter Ring Oscillator (SIRO) imnplemnentation in Field Programmable Gate Arrays (FPGAs), serving the purpose of on-chip oscillator driving co-existing clocked circutits is presented The property of SIRO to adapt to the FPGA technology by automatic frequency adjustment always ensures optimal performance of svnchronous circuit. Externally clocked(More)
  • Sohail Zafary, Bijan Jabbarix, Y. Zafar, xBijan Jabbari
  • 2007
A novel scheme for block-based motion compensation is introduced in which a block is classiied according to the energy that is directly related to the motion activity it represents. This classiication allows more exibility in controlling the bit rate and the signal-to-noise ratio and results in a reduction in motion search complexity. The method introduced(More)
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