Y. Trouiller

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This paper presents a complete 90nm CMOS technology platform dedicated to advanced SoC manufacturing, featuring 16 (27-70nm transistors (standard process) or 21-90nm transistors (Low Power process) as well as 2.5 or 3.3V I/O transistors, copper interconnects and SiOC low-k IMD (k=2.9). The main critical process steps are described and electrical results are(More)
Mask and metrology errors such as SEM (Scanning Electron Microscopy) measurement errors are currently not accounted for when calibrating OPC models. Nevertheless, they can lead to erroneous model parameters therefore causing inaccuracies in the model prediction if these errors are of the same order of magnitude than targeted modeling accuracy. In this(More)
Optical Proximity Correction (OPC) is used in lithography to increase the achievable resolution and pattern transfer fidelity for IC manufacturing. Nowadays, immersion lithography scanners are reaching the limits of optical resolution leading to more and more constraints on OPC models in terms of simulation reliability. The detection of outliers coming from(More)
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