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Continued scaling of DRAM technologies has required a limitation of the power dissipation from the peripheral region of the chip, while downscaling transistor oxide thickness and gate length. One route to enable further scaling, while circumventing excessive leakage currents, is the integration of high-κ metal-gate (HKMG) stacks into periphery and(More)
It is the first time that the high-k/metal gate technology was used at peripheral transistors for fully integrated and functioning DRAM. For cost effective DRAM technology, capping nitride spacer was used on cell bit-line scheme, and single work function metal gate was employed without strain technology. The threshold voltage was controlled by using single(More)
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