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Nano scale body-tied FinFETs have been firstly fabricated. They have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 60 nm. This Omega MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of(More)
The effects of TaN metal-gate thickness on the electrical characteristics of poly-Si/metal-gate/HfSiON MOSFETs have been investigated. Too thin TaN was reactive with poly-Si gate, which led to the formation of Si-doped metal gate. As a result, the work function of the metal gate was reduced and the capacitance increased while generating traps in HfSiON(More)
The SiGe SD structure in peripheral PMOS area of DRAM was successfully integrated without any degradation of peripheral NMOS properties, which is the first approach to DRAM. The PMOS performance enhancement was found to be more than 40%. The authors suggest the SiGe SD structure as the key solution for the improvement of peripheral PMOS transistor(More)
Electrostatic channel extension (ESCE) MOSFET, a transistor with static inversion layer formed by interface fixed charge is fabricated in planar bulk structure down to 20 nm gate-length. The 24 nm gate-length ESCE transistor with current 80 nm gate-length SRAM technology shows the excellent drive currents of 1.0 mA/mum with I<sub>OFF</sub> of 93 nA/mum at(More)
The plasma nitrided gate oxide process has been developed and applied for mobile DRAM with low operating voltage. As a result, we confirm that plasma nitrided gate oxide can block the boron penetration in DRAM, which has a higher thermal budget than other devices. The nitrogen bonding status and profile are investigated to check the change in transistor and(More)
A novel LOCOS type isolation technology, Nitride Cladded Poly-Si Spacer LOGOS (NCPSL) which is for the 1 giga bit DRAM, has been developed. The features of the NCPSL process are low bird's beak encroachment and long effective isolation length, which are achieved by using substrate silicon recess etching, poly-Si sidewall spacer, and selectively deposited(More)
Issues of ultrashallow junctions (USJ) for sub-50 nm gate-length transistors are discussed. To measure the actual current drivability of source/drain extension (SDE), we developed SDE sheet resistance test structure (SSTS) which simulates the actual geometry and thermal condition of dopant underneath sidewall spacer. By using low energy electron induced(More)
We have found that the defect generation which is induced by the mechanical stress during the densification, depends on the ratio of the trench filling material composed of the TEOS-O/sub 3/ based CVD oxide with tensile stress and the plasma enhanced CVD oxide with compressive stress. The lower as-deposited stress is, the lower the maximum stress during the(More)
The in-line plasma process monitoring was successfully performed with non-contact direct measurement (NCDM) tool and its results were well matched with those from devices. Using this monitoring method, we developed a plasma nitrided gate oxide process for mobile DRAMs with low operating voltage. We confirm that plasma nitrided gate oxide can block the boron(More)
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