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We report on gate-last technology for improved effective work function tuning with &#x223C;200meV higher p-EWF at 7&#x00C5; EOT, &#x223C;2x higher f<inf>max</inf> performance, and further options for channel stress enhancement than with gate-first by taking advantage of the intrinsic stress of metals and gate height dependence. Additional key features: 1)(More)
We report low V<inf>t</inf> (V<inf>t,Lg=1&#x00B5;m</inf>=&#x00B1;0.26V) high performance CMOS devices with ultra-scaled T<inf>inv</inf> down to T<inf>inv</inf>&#x223C;8&#x00C5; using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel(More)
We report on aggressively scaled RMG-HKL devices, with tight low-V<sub>T</sub> distributions [&#x03C3;(V<sub>Tsat</sub>) ~ 29mV (PMOS), ~ 49mV (NMOS) at L<sub>gate</sub>~35nm] achieved through controlled EWF-metal alloying for NMOS, and providing an in-depth overview of its enabling features: 1) physical mechanisms, model supported by TCAD simulations and(More)
This paper presents for the first time a low-complexity high performance CMOS HK/MG process on planar bulk Si using a single dielectric / single metal gate stack and making use of dual-channel integration. Through the optimization of the Si<inf>45</inf>Ge<inf>55</inf>/Si cap deposition and the workfunction metal, high performance devices with balanced(More)
In this work, we report high performance Si<inf>.45</inf>Ge<inf>.55</inf> Implant Free Quantum Well (IFQW) pFET with high drive current of 1.28mA/um at Ioff=160nA/um at channel length/width of 30nm/0.16um (Vdd=&#x2212;1V). This is enabled by 1) low temperature process which maintains the integrity of the high mobility of Si<inf>.45</inf>Ge<inf>.55</inf>(More)
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