Xueyi Yu

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Offering less than 1ppm frequency resolution, a ΔΣ fractional-N PLL enables flexible frequency planning and reliable spread spectrum modulation for digital clock generation [1, 2]. Use of low-cost ring VCOs however, mandates a wideband PLL design, which makes it difficult for the PLL to filter out high-frequency quantization noise from the ΔΣ modulator. In(More)
−In this paper, a novel architecture of a fractional-N phase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequential outputs of a ∆Σ modulator, finite impulse response (FIR) filtering with respect to modulator noise is realized in the PLL, resulting in quantization noise reduction in high(More)
This paper describes a quantization noise reduction method in ΔΣ fractional-N synthesizer design based on a semidigital approach. By employing a phase shifting technique, a low power hybrid finite impulse response (FIR) filtering is realized which is suitable for RF applications. A prototype fractional-N synthesizer is implemented in 180nm CMOS for(More)
As data rate of wireline applications increases, clock skew becomes a significant portion of the overall timing margin and directly affects the BER performance. A variable delay line (VCDL) or a DLL is widely used for elastic timing control not only in source-synchronous serial links but also in clock-and-data-recovery systems for further enhancing the BER(More)
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