Xueyi Yu

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This paper proposes a micro-system design for the wireless endoscopic capsule, which assures that the capsule has small size(less than 25mm<sup>*</sup>10mm), can implement the diagnoses of whole human digestive tract and provide real time endoscopic image monitoring. The designs of two core hardware parts inside the capsule, low power analog-digital(More)
Offering less than 1ppm frequency resolution, a ΔΣ fractional-N PLL enables flexible frequency planning and reliable spread spectrum modulation for digital clock generation [1, 2]. Use of low-cost ring VCOs however, mandates a wideband PLL design, which makes it difficult for the PLL to filter out high-frequency quantization noise from the ΔΣ modulator. In(More)
This paper describes a quantization noise reduction method in ΔΣ fractional-N synthesizer design based on a semidigital approach. By employing a phase shifting technique, a low power hybrid finite impulse response (FIR) filtering is realized which is suitable for RF applications. A prototype fractional-N synthesizer is implemented in 180nm CMOS for(More)
−In this paper, a novel architecture of a fractional-N phase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequential outputs of a ∆Σ modulator, finite impulse response (FIR) filtering with respect to modulator noise is realized in the PLL, resulting in quantization noise reduction in high(More)
This paper describes a quantization noise reduction method in DeltaSigma fractional-N synthesizer design based on a semidigital approach. By employing a phase shifting technique, a low power hybrid finite impulse response (FIR) filtering is realized which is suitable for RF applications. A prototype fractional-N synthesizer is implemented in 180 nm CMOS for(More)
This paper presents a low-noise &#x0394;&#x03A3; fractional-N PLL utilizing a mixed-mode triple-input LC VCO. An analog dual-path VCO control relaxes the nonlinearity problem of the &#x0394;&#x03A3; fractional-N PLL, while a combination of discrete and continuous tuning methods for coarse-tuning control significantly alleviates the noise coupling problem(More)
A semi-digital phase-interpolator based CDR is implemented in 0.18&#x00B5;m CMOS. By employing a cascaded architecture, versatile CDR operation is achieved. The first-stage CDR provides fast acquisition even with large initial frequency difference, followed by the second-stage CDR to further improve the time margin for phase tracking. An adaptive algorithm(More)