tested in a CLCC-68 package.
SFDR and narrow band SFDR are measured as 33 dBc and 42 dBc respectively. The measured phase noise with an output frequency of 1.57 GHz is 118.55 dBc/Hz at a 10 kHz frequency offset with a 7.2 GHz clock input generated from an Agilent E8257D analog signal generator. All the measurements were taken with the chips bonded in a CLCC-52 package.
—This paper presents a low power, high speed and high resolution SiGe DDS MMIC with 11-bit phase and 10-bit amplitude resolutions. Using more than twenty thousand transistors, including an 11-bit pipeline accumulator, a 6-bit coarse DAC and seven 3-bit fine DACs, the core area of the DDS is 3 × 2.5mm 2. The maximum clock frequency was measured at 8.6GHz… (More)
—This paper presents a low power, high speed SiGe DDS MMIC with 9-bit phase and 7-bit amplitude resolutions. This DDS MMIC is the first reported GHz range output DDS with direct digital frequency and phase modulation capabilities. Using more than eight thousand transistors, the DDS MMIC includes a 9-bit CLA accumulator for phase accumulation, a 9-bit CLA… (More)
—This paper presents a transformer-coupled varactor-less quadrature current-controlled oscillator (QCCO) RFIC covering the entire X-Band from 8.7 GHz to 13.8 GHz. The QCCO incorporates a transformer-coupled technique that achieves frequency tuning by varying the bias currents in the primary and secondary windings. Fabricated in a 0.18 m SiGe BiCMOS… (More)
— this paper presents an 8.7-13.8 GHz transformer-coupled varactor-less quadrature current-controlled oscillator (QCCO) RFIC. It incorporates a transformer-coupled technique and tuned by varying the operation current through the primary and secondary windings. Fabricated in a 0.13 µm SiGe BiCMOS process, the prototype QCCO achieves a 45.3% wide tuning… (More)
—This paper describes a 12-bit 300 MHz CMOS DAC for high-speed system applications. The proposed DAC consists of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q 2 random walk strategy. To minimize the feedthrough and… (More)
direct digital synthesis (DDS) for chirp generation is presented. The radar chip, including receiver, transmitter, quadrature DDS, phase-locked loop (PLL) and analog to digital converter (ADC), has been implemented in a 0.13μm BiCMOS technology. The stretch processing technique is employed to translate the time interval between the received and the… (More)
Author Affiliations and Mailing Addresses will be found on page 34.
chip consumes 326 mW in the receive mode and 333 mW in the transmit mode, respectively.