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This paper presents a self-testing and calibration method for the embedded successive approximation register (SAR) analog-to-digital converter (ADC). We first propose a low cost design-for-test (DfT) technique which tests a SAR ADC by characterizing its digital-to-analog converter (DAC) capacitor array. Utilizing DAC major carrier transition testing, the(More)
Integrator leakage is a dominant factor in the SNR (signal-to-noise ratio) loss of ΔΣ modulators. In this paper, we propose a Design-for-Test (DfT) technique to diagnose the integrator leakage of the single-bit first-order ΔΣ modulator. The proposed technique is a low-cost solution; it only adds two multiplexers to the modulator,(More)
Integrator leakage is a dominant factor in the SNR (signal-to-noise ratio) loss of ΔΣ modulators. In this paper, we propose a Design-for-Test (DfT) technique to diagnose the integrator leakage of the single-bit first-order ΔΣ modulator. The proposed technique is a low-cost solution; it only adds two multiplexers to the modulator,(More)
This paper presents a robust, low-cost ADC code hit counting technique to record the number of times each ADC output code word appears with respect to the ramp input. Using a smart center code tracking engine, the proposed code hit counter performs robustly against the code transition noise, missing code segments, and non-monotonicity; furthermore, the(More)