Xiongfei Meng

Learn More
&THE IC INDUSTRY is moving quickly to adopt new deep-submicron (DSM) technologies that offer unprecedented integration levels and cost benefits. Unfortunately, these advanced technologies pose new and sometimes unexpected challenges to the semiconductor industry. Current DSM problems of excessive power dissipation, voltage-drop effects, coupling noise, and(More)
On-chip decoupling capacitors (decaps) are widely used to reduce power supply noise by placing them at the appropriate locations on the chip between blocks. While passive decaps can provide a certain degree of protection against IR drop, if a problem is found after the physical design is completed, it is difficult to implement a quick fix to the problem. In(More)
On-chip decoupling capacitors are generally used to reduce power supply noise. Traditional decoupling capacitor designs using NMOS devices may no longer be suitable for 90nm CMOS technology due to increased concerns on thin-oxide gate leakage and electrostatic discharge (ESD) reliability. A cross coupled design for standard cells has recently been proposed(More)
We propose a novel circuit called charge-borrowing decap (CBD) as a drop-in replacement for passive decaps to reduce supply noise for removal of “hot-spot” IR-drop problems found late in the design process. Measurement results on a 90nm test chip show that a noise reduction improvement between 42%–55% at 100MHz-1.5GHz over its passive(More)
On-chip decoupling capacitors (decaps) in the form of MOS transistors are widely used to reduce power supply noise. This paper provides guidelines for standard cell layouts of decaps for use within Intellectual Property (IP) blocks in application-specific integrated circuit (ASIC) designs. At 90-nm CMOS technology and below, a tradeoff exists between(More)
Active decoupling capacitors (decaps) are more effective than passive decaps at reducing local IR-drop problems in the power distribution network. In the basic active decap, two parallel decaps are stacked in series whenever the voltage drop exceeds a given budget to boost the local supply voltage. However, the effectiveness of stacking three or more decaps(More)
On-chip decoupling capacitors (decaps) are widely used to reduce power supply noise. Typically, designs use NMOS decaps between standard-cell blocks and NMOS+PMOS decaps within the blocks. Starting at the 90nm CMOS technology node, the traditional decap designs may no longer be suitable due to increased concerns regarding thin-oxide gate leakage and(More)
  • 1