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—This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the(More)
Prior research efforts have been focusing on using BCH codes for error correction in multi-level cell (MLC) NAND flash memory. However, BCH codes often require highly parallel implementations to meet the throughput requirement. As a result, large area is needed. In this paper, we propose to use Reed-Solomon (RS) codes for error correction in MLC flash(More)
Long BCH codes are used as the outer error-correcting code in the second generation of Digital Video Broadcasting Standard from the European Telecommunications Standard Institute. These codes can achieve around 0.6dB additional coding gain over Reed-Solomon codes with similar codeword length and code rate in long-haul optical communication systems. BCH(More)
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate. For the first time, this paper proposes a partial-parallel decoder architecture based on the Min-max algorithm for quasi-cyclic NB-LDPC codes. A novel boundary tracking based scheme and corresponding(More)
—In this paper, a matrix permutation scheme is proposed to convert a generic QC-LDPC code to a shift-structured LDPC code. Thus, efficient VLSI architectures can be developed to achieve very high decoding throughput with low hardware complexity. Furthermore, novel implementation schemes for min-sum algorithm based column-layered decoding are presented. The(More)
Compressive sensing (CS) is a superior signal sampling strategy that combines sampling and compression. CS-based imaging systems include sampling and reconstruction stages. Currently, the complex task of image reconstruction has only been implemented in software, which can only achieve very limited speed. This paper proposes a high-speed hardware(More)
—In the hardware implementations of the Advanced Encryption Standard (AES) algorithm, employing composite field arithmetic not only reduces the complexity but also enables deep subpipelining such that higher speed can be achieved. In addition, it is more efficient to employ composite field arithmetic only in the SubBytes transformation of the AES algorithm.(More)
Unlike embryos derived from fertilization, most cloned embryos die during postimplantation development, and those that survive to term are frequently defective. Many of the observed defects involve placenta. Abnormal placentation has been described in several cloned species. Imprinted genes are important regulators of placenta growth, and may be subjected(More)