Xingchao Yuan

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—Accurate analysis of system timing and voltage margin including deterministic and random jitter is crucial in high-speed I/O system designs. Traditional SPICE-based simulation techniques can precisely simulate various deterministic jitter sources, such as intersymbol interference (ISI) and crosstalk from passive channels. The inclusion of random jitter in(More)
As the operating frequency of digital systems increases and voltage swing decreases, it becomes increasingly important to accurately characterize and analyze power distribution networks (PDN). This paper presents the modeling, simulation, and measurement of a PDN in a high-speed FR4 printed circuit board (PCB) designed for chip-to-chip communication at a(More)
Accurate analysis system timing and voltage margin at a target bit error rate across process, voltage, and temperature variations is required for high volume production of high speed systems. This in turn requires a statistical simulation framework to advanced signaling techniques such as transmitter equalization and receiver decision feedback. Furthermore,(More)